I'm currently an EECS Ph.D candidate at the University of Michigan, Ann Arbor and a member of the VLSI-SP Group advised by Professor Zhengya Zhang. I'm open to challenging opportunities before I conclude my PhD!
I received my M.S. degree in EE from the University of California, Los Angeles (UCLA) in 2015 and my B.S. degree in EE from National Tsing Hua University (NTHU). My research interest is in domain-specific computing architectures and system framework designs for accelerating machine learning, deep learning, computer vision and robotics. I have ASIC, SoC tape-out experiences in 0.18um, 40nm, 16nm and 14nm CMOS technologies. I have also built multi-camera-based PoCs for AIO products using commercial-grade FPGAs. I'm currently building an agile high-level-modeling (HLM) framework for modular and scalable domain-specific computing architecture exploration and development.
In 2018, I took a gap year from my Ph.D. to serve as a Technical Founding Partner of Iluvatar CoreX, an AI chip and systems startup based in the Silicon Valley and Greater China. In addition, I've worked as a full-time Research Scientist at Intel Labs from 2015 to 2016, held a Research Internship at Nvidia Research in 2017, a Graduate Technical Internship at Intel Labs in 2014, a Digital Design Internship at Silicon Image (Lattice) in 2014 and an SoC Design Internship at Skyviia in 2010.
EDUCATION
University of Michigan, Ann Arbor
Ph.D. in Electrical Engineering and Computer Science
May 2016 - Present
University of California, Los Angeles
M.S. in Electrical Engineering
Sep 2013 - May 2015
National Tsing Hua University
B.S. in Electrical Engineering
Sep 2008 - Jun 2012
WORK EXPERIENCES
Iluvatar CoreX (天数智芯)
Technical Founding Partner, Head of Advanced Technologies Group
Dec 2017 - Jan 2019
San Jose, CA, USA
Jun 2017 - Sep 2017
Santa Clara, CA, USA
Nvidia Research
Research Intern
Intel Labs
Senior Research Scientist
May 2015 - May 2016
Santa Clara, CA, USA
Intel Labs
Graduate Technical Intern
Sep 2014 - Dec 2014
Hillsboro, OR, USA
Silicon Image
ASIC Design Intern
Jun 2014 - Sep 2014
Sunnyvale, CA, USA
Skyviia
SoC Design Intern
Jun 2010 - Sep 2010
Hsinchu, TW
EXTRACURRICULAR
Wolverine Venture Fund
Student Advisor
Oct 2019 - Present
Ann Arbor, MI, USA
miLead Consulting Group
Consultant
Oct 2019 - Present
Ann Arbor, MI, USA
HONORS & AWARDS
Oct 2017
$50,000 Startup Award
TUS International Limited Gap Fund
$100,000 Startup Award
Michigan Translational Research and Commercialization (MTRAC)
Jun 2017
Sep 2016 - Sep 2020
Rackham Graduate Fellowship
University of Michigan, Ann Arbor
PUBLICATIONS
SNAP: A 1.67-21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network
Inference in 16nm CMOS
J-F. Zhang, C-E Lee, C. Liu, S. Shao, S. Keckler, Z. Zhang
2019 Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, 2019
A 135mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification
T.Chen, C-E Lee, Z. Zhang
Journal of Solid-State Circuits (JSSC) , 2019
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
C. Fu, S. Zhu, H. Su, C-E Lee, J. Zhao
International Symposium on Field-Programmable Gate Arrays (FPGA) 2019, Monterey Bay, US, 2019
Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
C-E Lee, S. Shao, J-F Zhang, A. Parashar, J. Emer, S. Keckler, Z. Zhang
Conference on Systems and Machine Learning (SysML), Stanford, US, 2018
A 127mW 1.63TOPS Sparse Spatio-Temporal Cognitive SoC for Action Classification and Motion Tracking in Videos
C-E Lee, T.Chen, Z. Zhang
2017 Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, 2017.
High-performance Spiking Neural Net Accelerators for Embedded Computer Vision Applications
JK. Kim, P, Knag, T. Chen, C. Liu, C-E Lee, Z. Zhang
IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, US, 2017
An Error-Compensated Piecewise Linear Logarithmic Arithmetic Unit for Phong Lighting Acceleration
C-E Lee, M.D. Ercegovac
IEEE Proc. 49th Asilomar Conference on Signals, Systems & Computers (ACSSC), Asilomar, US, 2015
Reconfigurable and Selectively-Adaptive Signal Processing for Multi-Mode Wireless Communication
F. Sheikh, O. Andersson, C-E Lee, F. Xue, C-H Chen, A. Vaidya, A. Sharma, T. Tetzlaff
IEEE International Workshop on Signal Processing Systems (SiPs), Hangzhou, China, 2015
PATENTS
Methods and Apparatus for Similar Data Reuse in Dataflow Processing Systems (pending)
Methods and Apparatus for Designing Flexible Dataflow Processor for Artificial Intelligent Devices (pending)
Two-Level, Fine-Grained Programmable Architecture to Accelerate Deep Learning Workloads (pending)
A Deep Neural Network Accelerator With Fine-Grained Parallelism Discovery
Sparse Video Inference Processor For Action Classification And Motion Tracking
Methods and Devices for Self-Interference Cancelation
RLS-DCD Adaptation Hardware Accelerator for Interference Cancellation in Full-Duplex Wireless Systems
Energy Efficient Polynomial Kernel Generation in Full-Duplex Radio Communication
